1. Field of the Invention
An electronic ballast converts a low frequency AC current as input to a high frequency current to the gas discharge lamp so that the lamp operates efficiently. Such ballast or converter is required to have low line input current harmonics as well as a high power factor in order to satisfy the stringent requirement regarding operating parameters. Many configurations have been proposed to achieve low input current distortion. Among them, so-called boost converter is a typical power factor correction converter. A boost converter, followed by a DC/AC inverter is able to provide a high frequency current fed to the lamp with power factor correction and low input current harmonics. However, the energy is processed in two separate conversion stages. As a result, the component count increases, which in turn causes the converter to be bulky and causes an increase in cost. In order to reduce costs, many integrated power factor correction stages with DC/AC inverters have been proposed.
2. Description of the Related Art
U.S. Pat. No. 5,274,540, hereby incorporated by reference, discloses a circuit shown in FIG. 1. Capacitor Cin is used to achieve power factor correction. Capacitor Cin integrates a power factor correction converter with a DC/AC inverter, composed of a half-bridge switches S1 and S2, and a series resonant tank of inductor Lr and capacitor Cr so that the component count is reduced, thereby reducing costs. The equivalent circuit of FIG. 1 is shown in FIG. 2, where the lamp voltage is considered as a high frequency voltage source. Charge capacitor Cin is in series with a high frequency voltage to charge capacitor Cin through the line input and to discharge the capacitor energy to bulk capacitor C.sub.B so that power factor correction can be achieved. There are four mode operations over one switching cycle. The switching waveforms are shown in FIG. 3.
Mode 1 t.sub.0, t.sub.1 !: Before time t.sub.0, voltage .nu..sub.m is clamped to voltage V.sub.dc, and diode Dy is on. After time t.sub.0, voltage .nu..sub.a decreases with a sinusoidal waveform. Since the charge capacitor voltage .nu..sub.c can not change abruptly, diode Dy is in reverse bias, and voltage .nu..sub.m also decreases with the same form. Voltage .nu..sub.m at this time is still higher than the rectified line voltage, diode Dx is reverse biased, voltage .nu..sub.c keeps constant because there is no current through capacitor Cin and both diodes Dx and Dy are off. This mode ends at time t.sub.1, where the voltage .nu..sub.m is equal to the rectified line voltage. Diode Dx becomes forward-biased, and begins to conduct.
Mode 2 t.sub.1, t.sub.2 !: At time t.sub.1, diode Dx is turned on, and voltage .nu..sub.m is clamped to the rectified line voltage. Since voltage .nu..sub.a continues to decrease, the charge capacitor voltage .nu..sub.c increases to V.sub.a +.vertline..nu..sub.in .vertline. at time t.sub.2. During this time interval, the charge capacitor absorbs energy from the line input. Its voltage and charging current are determined by: ##EQU1## where .omega.s and Va are the frequency and the peak voltage of the voltage source .nu..sub.a, respectively. At time t.sub.2, current i.sub.x becomes zero, and diode D.sub.x is naturally turned off. The maximum charge capacitor voltage V.sub.c, max is EQU V.sub.c, max=V.sub.a +.vertline.V.sub.in .vertline.. (2)
Mode 3 t.sub.2, t.sub.3 !: At time t.sub.2, diode Dx is turned off. Because voltage .nu..sub.m is lower than the DC bus voltage, diode Dy is in the reverse bias. No current flows through the charge capacitor Cin and voltage .nu..sub.c keeps constant. On the other hand, voltage .nu..sub.m continuously increases with the increase of voltage .nu..sub.a until time t.sub.3, where voltage .nu..sub.m reaches the DC bus voltage, and diode Dy is turned on.
Mode 4 t.sub.3, t.sub.4 !: At time t.sub.3, voltage .nu..sub.m is clamped to the DC bus voltage, and diode Dy is turned on. Charge capacitor Cin discharges, and its energy is pumped to capacitor C.sub.B due to the continuous increase of voltage .nu..sub.a. The charge capacitor voltage and its charging current are ##EQU2## Voltage .nu.c reaches its minimum value at time t.sub.4, which is given by EQU V.sub.c,min =V.sub.dc -V.sub.a. (4)
At time t.sub.4, voltage .nu..sub.a increases to its peak voltage. Diode Dy will be turned off; and next switching cycle begins.
From the above analysis, it can be seen that the rectified AC line current is equal to the capacitor charging current during the time period from time t.sub.1 to time t.sub.2. Therefore, the average C line current over one switching cycle equals the average capacitor charging current, which is the total charge variation from time t.sub.1 to time t.sub.2. The charge variation of capacitor Cin is EQU .DELTA.Q=Cin(V.sub.c,max -V.sub.c,min) (5)
Substituting voltages V.sub.c,max and V.sub.c,min into equation (5) yields the rectified line current in a switching cycle, given by ##EQU3##
The input power P.sub.in is the average value of the product of voltage .nu..sub.in and current i.sub.in over one line cycle, which is ##EQU4## where V.sub.in,p is the line peak voltage. During the preheat and start-up operations, the lamp is not turned on. The output power P.sub.0 of the circuit is smaller than that of the normal operation. The switching frequency at preheat mode is higher than that of normal lighting frequency, and the lamp voltage 2V.sub.a at start-up mode is much higher than that of normal lighting operation. In order to maintain the relationship shown in equation (7), the DC bus voltage V.sub.dc has to increase at preheat and start-up modes. Therefore, one of the main disadvantages is high DC bus voltage stress at preheat and start-up mode operations. As a result, high voltage bulk capacitor and high voltage rating power devices must be used, which increase the cost of the device. Another main disadvantage is the high lamp crest factor. Usually, the higher the lamp crest factor, the shorter the lamp life. The high crest factor of the circuit of FIG. 1 is mainly due to a modulation of capacitor Cin on the resonant tank. Capacitor Cin is equivalently in parallel with the resonant capacitor Cr when either diode Dx or diode Dy is on. The equivalent resonant tank of FIG. 1 is shown in FIG. 4A. The equivalent resonant capacitor is Cr, and capacitors Cr+Cin near the zero crossing of the line input voltage and near the line peak voltage, respectively. Since capacitor Cin is much higher than capacitor Cr, the equivalent resonant capacitor of FIG. 1 significantly changes over the line cycle. As a result, the lamp crest factor becomes high at constant frequency and constant duty ratio control. Another disadvantage is that the rectified line current through diode Dx is discontinuous, thereby requiring a large line input filter to be used.
U.S. Pat. No. 5,410,466, also hereby incorporated by reference, discloses the same basic circuit as shown in FIG. 1 by adding a new control for controlling the switching frequency and duty ratio of two switches S1 and S2 to achieve smooth lamp current with a constant envelope and low crest factor. However, the circuit of U.S. Pat. No. 5,410,466 still suffers from high DC bus voltage stress at preheat and start-up modes and discontinuous line input current so that a large line input filter has to be used.
To reduce the DC bus voltage stress at start-up for the circuit of FIG. 1, one alternative is to reduce voltage .nu..sub.a at preheat and start-up modes. The method is disclosed in a paper entitled "Reduction of voltage stress in charge pump electronic ballast," published in IEEE Power Electronics Specialist Conference Proceedings, pp. 887-893, 1996. The circuit is shown in FIG. 5, where a second resonance, composed of inductor Lr.sub.2 and capacitor Cr.sub.2, is inserted to the circuit of FIG. 1. During preheat and start-up modes, the switching frequency is close to the second resonant frequency of inductor Lr.sub.2 and capacitor Cr.sub.2 so that a low impedance is connected and voltage .nu..sub.a is reduced, while still obtaining enough lamp voltage to ignite the lamp. Therefore, the DC bus voltage V.sub.dc can be reduced. By adding two clamping diodes Dr.sub.1 and Dr.sub.2, unity power factor can be achieved and also a low lamp crest factor can be simultaneously achieved. However, two resonant inductors must be used, which increases the cost of the device. Furthermore, the switch suffers from high current stress. This switching current is about one and one-half times the switching current of the circuit of FIG. 1. Therefore, devices having a high current rating must be used, which also increases the cost of the device.
Other known devices are disclosed in U.S. Pat. Nos. 5,404,082 and 5,410,221. The circuits of these two patents are shown in FIG. 6A. Capacitor Cin is in parallel with diode Dy to suppress the input current distortion and achieve a high power factor. The construction of FIG. 6A is different from FIG. 1. The equivalent circuit of FIG. 5 can be expressed as FIG. 7, where the series resonant tank is considered a high frequency current source with a constant amplitude. There are four operational modes for the circuit of FIG. 6A, as illustrated in FIGS. 6B-6E. The four equivalent topological stages and switching waveforms are shown in FIGS. 6B-6E.
Mode 1 t.sub.0 .about.t.sub.1 !: As shown in FIGS. 6B and 8, before time t.sub.0, the source current i.sub.s has a negative value, and it flows through the diode Dy. The voltage at node m is clamped to the bus voltage V.sub.dc. At time t.sub.0, source current i.sub.s becomes positive and begins to charge capacitor Cin The charge capacitor voltage .nu..sub.c begins to rise while voltage .nu..sub.m decreases. So, charge capacitor Cin accumulates energy from the DC bus. This mode terminates at time t.sub.1, where the voltage at node m decreases to the line input voltage, and diode Dx starts to conduct. The time interval t.sub.1 is determined by: ##EQU5## where .omega..sub.s is the frequency of source current i.sub.s, and V.sub.dc is the voltage across the bulk capacitor C.sub.B. The total charge variation in capacitor Cin is given by: EQU .DELTA.Q=C.sub.in (V.sub.dc -.vertline.V.sub.in .vertline.).(9)
There is no input line current during this stage.
Mode 2: t.sub.1, t.sub.2 !: Referring to FIGS. 6C and 8, at time t.sub.1, diode Dx begins to turn on and voltage .nu..sub.m is clamped to the rectified line input voltage. Source current i.sub.s flows through the line input and diode Dx. Therefore, the high frequency source current i.sub.s flows through the line input and diode Dx. Therefore, the high frequency source current i.sub.s absorbs energy directly from the AC line. At t.sub.2 =T.sub.s /2, source current i.sub.x becomes negative, while diode Dx is naturally turned off, and this mode ends. During this time interval, the rectified line current i.sub.x is given by: EQU i.sub.x =i.sub.s =I.sub.s sin .omega..sub.s t t.sub.1 &lt;t&lt;t.sub.2( 10)
Mode 3 t.sub.2, t.sub.3 !: As illustrated in FIGS. 6D and 8, at time t.sub.2, source current i.sub.s becomes negative and diode Dx is naturally off. Since voltage .nu.m is still lower than the DC bus voltage V.sub.dc, diode Dy cannot be turned on at this time. Source current i.sub.s is discharging capacitor Cin and the voltage at node m increases. Voltage .nu..sub.m rises to the DC bus voltage, where diode Dy starts to conduct at time t.sub.3.
Mode 4 t.sub.3, t.sub.4 !: As shown in FIGS. 6E and 8, at time t.sub.3, diode Dy begins to flow the current source i.sub.s, and the voltage at node m is clamped to the DC bus voltage until i.sub.s becomes positive, and diode Dy is naturally turned off at time t.sub.4 =Ts. The rectified input line current equals the average diode current i.sub.x over one switching cycle, which is given by: ##EQU6## where Ts is the switching period. After substituting i.sub.s into the above equation, we have ##EQU7## where .DELTA.Q is the charge variation of capacitor Cin and .DELTA.Q=Cin(V.sub.dc -.vertline..nu..sub.in .vertline.. Therefore, the rectified line current i.sub.x in one switching period is ##EQU8##
In order to achieve the unity power factor, the average input current should be proportional to the line input voltage. The first term of the above equation should be zero, which is given by EQU I.sub.s =.pi.C.sub.in f.sub.s V.sub.dc. (14)
This equation (14) is the unity power factor condition. The equation (13) becomes EQU i.sup.ave.sub.x =C.sub.in f.sub.s .vertline.V.sub.in .vertline..(15)
Equation (15) shows that the unity power factor can be obtained as long as equation (14) can be satisfied. The input power is the average value of the product of voltage .nu..sub.in and current i.sub.in over one line cycle, which is ##EQU9##
During the preheat and start-up operations, the lamp is not turned on. The output power P.sub.0 of the circuit is smaller than that of the normal operation. The switching frequency at preheat mode is higher than that of normal lighting frequency, and the circulating current at light load during the start-up mode is much higher than that of normal lighting operation. In order to maintain equation (16), the DC bus voltage V.sub.dc must increase at preheat and start-up modes. Therefore, one of the main disadvantages is a high DC bus voltage stress at preheat and start-up mode operations. This basic problem is the same as the circuit of FIG. 1. For the circuit of FIG. 6A, when diode Dy is conductive, capacitor Cin is shorted. The resonant tank consists of inductor Lr, capacitors Cr and Cin when both diodes Dx and Dy are non-conductive. Therefore, this circuit also has two resonant modes in one switching cycle, which causes the same problem that an envelope of the lamp current varies with the line input voltage. As a result, the lamp crest factor increases and the lamp life becomes shorter. Although U.S. Pat. Nos. 5,404,082 and 5,410,021 proposes a control scheme to suppress the lamp crest factor, the DC bus voltage stress at the preheat and start-up mode still exists, which requires high voltage rating bulk capacitor C.sub.B and power switches S1 and S2. Besides, the input current is discontinuous so that a large line input filter must be used.
U.S. Pat. No. 4,511,832 discloses a circuit as shown in FIG. 9. The input inductor Li and capacitor Ci are used to suppress line input current harmonics and reduce the input current ripple. Capacitor C1 provides a path to absorb energy from the line input every switching cycle, while capacitor C2 provides another path to the bulk capacitor for the series resonant parallel-loaded tank composed of inductor Lr and capacitor Cr. The DC bus voltage V.sub.dc across the bulk capacitor C.sub.B is suppressed by conducting the thyristor T when the DC bus voltage exceeds a certain value. Thus, the cost increases and the control circuit becomes complicated.
Japanese Patent No. P0-222469 discloses a lamp driving circuit shown in FIG. 10. The main purpose of adding inductor Li is to improve a total harmonic distortion (THD), reduce line input current harmonics. Inductor Li is used as a boost inductor. The current through inductor Li can flow through diode Dy to charge the bulk capacitor C.sub.B, without flowing through the power switch. So, the switching current stress of switches S1 and S2 becomes small. But, there is still a high DC bus voltage stress across the bulk capacitor C.sub.B at start-up mode so that high voltage rating bulk capacitor and power switches must be used, which significantly increases cost. Besides, the high crest factor also still exists.
Another prior art is disclosed in Japanese Patent No. P06-284748, the circuit of which is shown in FIG. 11. This circuit is basically the same as the circuit of FIG. 6A except for the addition of an input inductor Li. Input inductor Li is used to minimize the input line current ripple so that a small input filter can be used. Diode D1 is used to improve THD. However, this circuit still suffers from high DC bus voltage across C.sub.B at the start-up mode and also from high lamp crest factor at normal light operation.
U.S. Pat. No. 5,521,467 discloses the use of an inverter for supplying a high frequency energy to the lamp. The circuit is shown in FIG. 12. An inductor Li and a full wave rectifier composed of diodes D.sub.1 -D.sub.4 are provided to achieve high power factor. Capacitor C1 and inductor Li form a low pass filter so that the input rectified current through inductor Li is continuous. The function of capacitor C.sub.g is like capacitor Cin in the circuit of FIG. 1, while the function of capacitor C.sub.s is similar to capacitor Cin in the circuit of FIG. 6A. The main disadvantage is that high DC bus voltage across capacitor C.sub.B at the start-up mode. For the circuit FIG. 12, the circuit is shut down once the DC bus voltage exceeds a set value through the control circuit. Another drawback is that the component count is not reduced, compared with those of the two-stage approach. As a result, the cost cannot be reduced.
All these prior circuits are designed only with +10% line input voltage variation. They suffer from a large lamp power variation, high lamp crest factor, high THD, and high DC bus voltage stress at the start-up over a wide range line input voltage. Therefore, different designs must be taken for the different line input voltages. As a result, the circuit components are made different. The research and product development cycle becomes longer, which also increases the cost of the device.